1. Field of the Invention
The invention relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device having strain films and a method of manufacture.
2. Background Description
Metal-oxide semiconductor (MOS) transistors generally include a substrate made of a semiconductor material, such as silicon. The transistors also include a source region, a channel region and a drain region within the substrate. The channel region is located between the source and the drain regions. A gate stack, which includes a conductive material gate or gate conductor on top of a gate oxide layer and sidewall spacers, is provided above the channel region. More particularly, the gate oxide layer is provided on the substrate over the channel region, while the gate conductor is provided above the gate oxide layer. The sidewall spacers help define locations of source and drain ion implantation and form self-aligned silicide.
The amount of current flowing through a channel of a semiconductor device is proportional to the mobility of the carriers in the channel. Thus, the operation speed of the transistor can be increased by increasing the mobility of the carriers in the channel. To this end, mechanical stresses within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. The mechanical strain can be induced by, for example, distinct processes and/or materials to create tensile or compressive strains in the NFETs and PFETs, respectively.
To maximize the performance of both NFETs and PFETs within integrated circuit (IC) chips, the strain components should be engineered and applied differently for the NFETs and PFETs. That is, because the type of strain which is beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET. More particularly, when a device is in tension (in the direction of current flow in a planar device), the performance characteristics of the NFET are enhanced; whereas, this same strain component would negatively affect the performance characteristics of the PFET.
In one processing example, e-SiGe (embedded silicon germanium) in source and drain regions can be used to induce a compressive strain in PFETs (e.g., as the compressive strain improves hole mobility). However, the growth of the e-SiGe requires the NFET to be covered with a nitride cap mask. This allows a trench to be etched in the PFET so that the SiGe can be grown within the source and drain regions of the PFET, while ensuring that the SiGe is not grown in the source and drain regions of the NFET.
The masking of the NFET is necessary during the SiGe growth process so as to ensure that the e-SiGe will not affect the device performance of the NFET (i.e., a compressive strain in the source and drain regions of the NFET will degrade electron mobility and thus degrade performance of the NFET.) Additionally, the nitride layer used to cover the NFET must be subsequently etched without etching the exposed SiGe in the PFET source and drain regions. Of course this creates additional fabrication steps, leading to increased manufacturing complexities and additional manufacturing costs. Moreover, utilizing the nitride layer to cover the NFET has implications in terms of the process window allowed for the thickness of the nitride layer and makes the overall process flow more complicated.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.